高速低复杂度可重构L&R算法研究与实现

doi:10.12305/j.issn.1001-506X.2022.05.31

摘要/Abstract

摘要：

为满足卫星有效载荷数据传输系统高速、高可靠性的需求, 提出一种基于L&R(Luise and Reggiannini)算法的高速低复杂度可重构频偏恢复实现方案。为便于算法逻辑架构实现, 对算法的函数功能进行分解及模块化设计; 为减少乘法器资源消耗, 采用复用分解的自相关函数模块; 为提高L&R算法的精度, 对导频段自相关函数进行多段叠加。结果表明, 高速低复杂度可重构频偏恢复实现方案解调性能损失接近为0 dB, 且优化后的算法结构相比于直接结构可减少92.59%的乘法器消耗, 拆分的自相关函数功能模块具有可复用性和重构性。该算法的可工作时钟速率高达370.37 MHz, 在高速接收机中具有极高的应用价值。

关键词: 高速, 低复杂度, 可重构, 分解, 模块化, 累加器

Abstract:

A high-speed, low-complexity, reconfigurable frequency offset recovery implementation scheme based on the L&R (Luise and Reggiannini) algorithm is proposed to meet the high-speed and high-reliability requirements of the satellite payload data transmission system. The function of the algorithm is decomposed and modularized to facilitate the implementation of the algorithm logic architecture. The decomposed autocorrelation function modules are reused to reduce the resource consumption of the multiplier. The autocorrelation function of the pilot is superimposed in multiple sections to improve the accuracy of the L&R algorithm. The results show that the demodulation performance loss of the high-speed, low-complexity, reconfigurable frequency offset recovery scheme is close to 0 dB. Compared with the direct structure, the optimized algorithm can reduce the multiplier consumption by 92.59%, and the decomposed autocorrelation function module has reusability and reconfiguration. The algorithm can work at operating frequency up to 370.37 MHz, which has an extremely high application value in high-speed receivers.

Key words: high-speed, low-complexity, reconfigurable, decomposition, modular, accumulator

中图分类号:

TN911

胡婉如, 王竹刚, 梅如如, 陈轩. 高速低复杂度可重构L&R算法研究与实现[J]. 系统工程与电子技术, 2022, 44(5): 1685-1693.

Wanru HU, Zhugang WANG, Ruru MEI, Xuan CHEN. Research and implementation of high-speed and low-complexity reconfigurable L&R algorithm[J]. Systems Engineering and Electronics, 2022, 44(5): 1685-1693.

图/表 15

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算法类别	理论频偏估计范围
Kay算法	\|Δf\|＜$\frac{1}{{2{T_s}}}$
C&S算法	\|Δf\|＜$\frac{1}{{2{T_s}}}$
Fitz算法	\|Δf\|＜$\frac{1}{{2{T_s}}}$
L&R算法	\|Δf\|＜$\frac{1}{{2{T_s}}}$
M&M算法	\|Δf\|＜$\frac{1}{{2{T_s}}}$
Jiang算法	\|Δf\|＜$\frac{1}{{2{T_s}}}$

调制方式	符号速率/ MHz	频偏/ MHz	相偏/ (°)	码长	帧长
16APSK(r=2.85)	250	5	2	8 160	2 166

计算复杂度	L&R 算法^[15] (N=9)	改进 M&M 算法^[16] (M=9)	L&R 算法^[16] (N=18)	直接结构： L&R算法 (N=17)	改进结构：高速低复杂度可重构 L&R算法 (N=17)
乘法器	288	287	477	459	34
反正切	1	1	1	1	1

FPGA资源消耗情况	LUT	FF	BRAM	DSP
资源消耗个数	5 488	8 330	7.5	68
资源消耗占比/%	2.26	1.72	1.25	3.54

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