Abstract: In order to solve the application limitations of fully digital delay-locked loop (FDDLL) in high speed signal synchronization, this paper proposes a synchronization algorithm based on the combination of analog and digital domains. Highspeed gate circuits and active resistance-capacitance (RC) integrators are utilized to accomplish the correlation calculation between high speed analog signals and local regenerated signals. After sampling through low-speed analog to digital, interpolating, and loop filter, the digital output is used to estimate the transmitting delay, which is applied to adjust the regenerated signal. In this way, a closed synchronization loop mixed of analog and digital domains is generated, which can realize maintaining tracking of high speed signals. Both simulation and analysis results show that for the signal of transmission rate 2.5 Gsps, synchronization accuracy within 80 ps can be achieved through the proposed algorithm when Eb/N0 is higher than -10 dB, which is comparable to FDDLL. Meanwhile, compared with FDDLL, the proposed algorithm requires much lower sampling rate, which leads to a significant decrease of computational complexity of the digital signal processor. It saves clock and processing resources. Also power consumption is notably reduced through the proposed loop algorithm. It is more suitable for high speed transmission system.