不完美硬件实现对下行NOMA短包通信的影响

doi:10.12305/j.issn.1001-506X.2025.01.30

摘要/Abstract

摘要：

为了实现超可靠低延时通信(ultra-reliable and low latency communication, URLLC), 研究在Nakagami-m和莱斯衰落信道下硬件损伤(hardware impairment, HI)、信道估计误差(channel estimation error, CEE)以及不完美连续干扰抵消(successive interference cancellation, SIC)对下行两用户非正交多址接入(non-orthogonal multiple access, NOMA)短包通信(short packet communication, SPC)系统性能的影响。首先, 给出两种信道下用户的平均块错误率(block error rate, BLER)表达式。其次, 在用户的平均BLER要求限定下, 提出一种联合优化功率分配和导频序列长度的优化算法。最后, 仿真结果验证了理论推导的准确性, 并表明HI、CEE和不完美SIC对NOMA SPC系统性能具有大的影响; 为了NOMA SPC系统实现URLLC, 存在一个功率分配和导频序列长度的折中优化。

关键词: 非正交多址接入, 硬件损伤, 信道估计误差, 不完美连续干扰抵消, 短包通信

Abstract:

To achieve ultra-reliability and low-latency communication (URLLC), the impacts of hardware impairment (HI), channel estimation error (CEE) and imperfect successive interference cancellation (SIC) on the performance of downlink two-user non-orthogonal multiple access (NOMA) system with short packet communication (SPC) over Nakagami-m and Rician fading channels are investigated. Firsty, the expressions of average block error rate (BLER) for the users over these two channels are given. Then, under the constraints of users' average BLER, an optimization algorithm, which jointly optimizes the power allocation and the length of pilot sequence, is proposed. Finally, the simulation results verify the accuracy of the analytical results, and show that HI, CEE and imperfect SIC have a great influence on the performance of NOMA SPC system. Moreover, there exists a tradeoff optimization between the power allocation and the length of pilot sequence to accomplish URLLC for NOMA SPC system.

Key words: non-orthogonal multiple access (NOMA), hardware impairment (HI), channel estimation error (CEE), imperfect successive interference cancellation (SIC), short packet communication (SPC)

中图分类号:

TN92

莫名秀, 袁磊, 雷妍, 袁花花. 不完美硬件实现对下行NOMA短包通信的影响[J]. 系统工程与电子技术, 2025, 47(1): 296-306.

Mingxiu MO, Lei YUAN, Yan LEI, Huahua YUAN. Impact of imperfect hardware implementation on downlink NOMA short packet communication[J]. Systems Engineering and Electronics, 2025, 47(1): 296-306.

图/表 7

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